1. Field of the Invention
The present invention is in the field of digital logic circuits.
2. Description of the Related Art
Generally, digital logic systems operate on a synchronous basis. That is, the circuits within the digital logic system are responsive to a common "clock" signal such that output signals generated by a first logic circuit within the system change at predictable times with respect to the clock signal. Thus, a second logic circuit receiving an output signal from the first logic circuit can gate the output signal at a particular time with respect to the clock signal. In this manner, it is assured that the output signal is stable, e.g., has reached one of two binary states and has been at that state for a sufficient amount of time that the second logic circuit will detect the correct state.
It may be advantageous to selectively disable a number of circuits within a digital logic system for a specific time period. One method of accomplishing this would be to gate on and gate off the common clock input to a group of synchronous circuits using a control signal. For example, the clocking of bits through a shift register comprising a number of interconnected bistable components could be controlled by selectively disabling the clock inputs to each of these bistable components. A gating function accomplished by, for example, "ANDing" the clock with a "disable" signal such that when the disable signal is asserted the clock signal does not pass through to the gate output, however, may generate "glitches" in the clock signal, particularly if there is any uncertainty as to the times at which the disable signal changes with respect to the clock signals. This condition can especially arise when the enable signal is synchronously generated with respect to the clock to be gated. These glitches occur when the disable signal is asserted shortly after the rising or falling edges of the clock, resulting in narrowed clock pulses or possibly even "spikes" which can cause malfunctions in the clocked logic circuits. Thus, a need exists for a logic circuit that provides the benefits of a clock which can be enabled and disabled without generating such glitches.